1. Field of the Invention
The present invention relates to a technology for reducing a hardware amount and power consumption of a vector processor by providing a vector load buffer function to a cache memory.
2. Description of Related Art
As shown in FIG. 7, a vector processor of the related art includes a vector load buffer 212 (VLDB: Vector Load Buffer) between a vector register 201 and a memory unit 220. The vector load buffer 212 aligns a vector data being returned from the memory unit 220 at irregular timing, and provides the aligned vector data to a vector processing unit 200. The vector load buffer 212 reads the vector data in advance from the memory unit 220 for concealing a memory latency even if the vector register 201 is being used (i.e., in a “busy state”). The vector load buffer 212 is described in patent document 1. An alignment determination circuit 211 is a circuit for notifying the vector processing unit 200 that all the requested vector data are gathered in the vector load buffer 212.
On the other hand, a cache memory of a scalar processor is configured so that the cache memory returns requested data to a register of the scalar processor as often as the scalar processor requires the data. In other words, the cache memory of the scalar processor returns the data piece-by-piece (one element by one element in a serial manner) every time the data is requested by the scalar processor.    [Patent Document 1] Japanese Patent Laid-Open No. 02-101576